Novel circuit techniques for zero-power 25-ns CMOS erasable programmable logic devices (EPLDs)
- 1 October 1986
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Journal of Solid-State Circuits
- Vol. 21 (5) , 766-774
- https://doi.org/10.1109/jssc.1986.1052605
Abstract
No abstract availableKeywords
This publication has 4 references indexed in Scilit:
- A 100ns 256K CMOS EPROMPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2005
- A 50ns 48-term erasable programmable logic arrayPublished by Institute of Electrical and Electronics Engineers (IEEE) ,1985
- PROM Cell made with an EPROM processPublished by Institute of Electrical and Electronics Engineers (IEEE) ,1983
- A fault-tolerant 30 ns/375 mW 16Kx1 NMOS static RAMIEEE Journal of Solid-State Circuits, 1981