A fault-tolerant 30 ns/375 mW 16Kx1 NMOS static RAM
- 1 October 1981
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Journal of Solid-State Circuits
- Vol. 16 (5) , 435-443
- https://doi.org/10.1109/JSSC.1981.1051619
Abstract
A fault-tolerant 30950 mil/SUP 2/ (19.9 mm/SUP 2/) 16K/spl times/1 static MOS RAM has been fabricated with a single polysilicon E/D NMOS process. Using circuit techniques normally restricted to dynamic RAMs, but adapted for asynchronous operation, the device achieves a typical access time of 30 ns while dissipating only 375 mW. Among the topics discussed in a new single-polysilicon memory cell configuration, the first truly asynchronous bootstrap circuit, an active bit-line equilibration and precharge scheme, and a new power-efficient substrate bias generator. Also described is an on-chip redundancy scheme which consumes approximately 2 percent of the total chip area, does not compromise access time and can be programmed using standard test equipment.Keywords
This publication has 3 references indexed in Scilit:
- 2K×8b HCMOS static RAMsPublished by Institute of Electrical and Electronics Engineers (IEEE) ,1980
- A 64Kb static RAMPublished by Institute of Electrical and Electronics Engineers (IEEE) ,1980
- A high-performance MOS technology for 16K static RAMPublished by Institute of Electrical and Electronics Engineers (IEEE) ,1979