A 700-Mb/s/pin CMOS signaling interface using current integrating receivers
- 1 May 1997
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Journal of Solid-State Circuits
- Vol. 32 (5) , 681-690
- https://doi.org/10.1109/4.568834
Abstract
A high speed CMOS signaling interface for application in multiprocessor interconnection networks has been developed. The interface utilizes I-V push-pull drivers, a delay line phase-locked loop (PLL), and sampling of the data on both edges of the clock. In order to increase the noise immunity of the reception, a current-integrating input pin sampler is used to receive the incoming data. Chips fabricated in a 0.8 μm CMOS technology achieve transfer rates of 740 Mb/s/pin operating from a 3.3 V supply with a bit error rate of less than 10-14Keywords
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