High-level test generation for VLSI
- 1 April 1989
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in Computer
- Vol. 22 (4) , 16-24
- https://doi.org/10.1109/2.25379
Abstract
The authors survey high-level approaches to test generation for VLSI circuits, which can significantly reduce test generation time while still providing good fault coverage. High-level approaches view the circuit with less structural detail, that is, from a more abstract viewpoint and often hierarchically. The authors first review some basic circuit and fault models and the two most widely known test-generation algorithms as a basis for comparison between high-level and low-level techniques. The authors then examine the more important high-level approaches, which fall into two broad classes, namely algorithmic and heuristic.Keywords
This publication has 8 references indexed in Scilit:
- Hierarchical test generation using precomputed testsd for modulesPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2003
- Expert system for the functional test program generation of digital electronic circuit boardsPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2003
- A hierarchical approach test vector generationPublished by Association for Computing Machinery (ACM) ,1987
- An Artificial Intelligence Approach to Test GenerationPublished by Springer Nature ,1987
- Logic Testing and Design for TestabilityPublished by MIT Press ,1985
- Testing Strategy and Technique for Macro-Based CircuitsIEEE Transactions on Computers, 1985
- Test Generation Algorithms for Computer Hardware Description LanguagesIEEE Transactions on Computers, 1982
- Test Generation for MicroprocessorsIEEE Transactions on Computers, 1980