Testing Strategy and Technique for Macro-Based Circuits
- 1 January 1985
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Computers
- Vol. C-34 (1) , 85-90
- https://doi.org/10.1109/TC.1985.1676519
Abstract
The increasing complexity of VLSI systems demands structured approaches to reduce both design time and test generation effort. PLA's and scan paths have both been widely reported to be efficient in this sense. This correspondence presents an easily testable structure and its related testing strategies. The circuits are assumed to be based on the interconnection of combinatorial macros, mostly implemented by PLA's; tests are generated locally, considering the involved macro as an isolated item, and then are expressed in terms of primary inputs and outputs using a topological approach as general strategy and algebraic techniques for the propagation of signals through macros. Propagation is dealt with by new algorithms. Since the problem of test generation is NP-hard, a set of heuristics is introduced to keep the amount of computation reasonable; several implementation issues are finally investigated.Keywords
This publication has 8 references indexed in Scilit:
- PART: Programmable Array Testing Based on a Partitioning AlgorithmIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1984
- VLSI Processor ArchitecturesComputer, 1982
- A Design of Programmable Logic Arrays with Universal TestsIEEE Transactions on Computers, 1981
- A Hardware Approach to Self-Testing of Large Programmable Logic ArraysIEEE Transactions on Computers, 1981
- A structured design methodology and associated software toolsIEEE Transactions on Circuits and Systems, 1981
- Silicon Compilation-A Hierarchical Use of PLAsPublished by Institute of Electrical and Electronics Engineers (IEEE) ,1979
- Efficient Algorithms for Testing Semiconductor Random-Access MemoriesIEEE Transactions on Computers, 1978
- Diagnosis of Automata Failures: A Calculus and a MethodIBM Journal of Research and Development, 1966