Directional bias and non-uniformity in FPGA global routing architectures
- 23 December 2002
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
Abstract
We investigate the effect of the prefabricated routing track distribution on the area-efficiency of FPGAs. The first question we address is whether horizontal and vertical channels should contain the same number of tracks (capacity), or if there is a density advantage with a directional bias. Secondly, should the channels have a uniform capacity, or is there an advantage when capacities vary from channel to channel? The key result is that the most area-efficient global routing architecture is one with uniform (or very nearly uniform) channel capacities across the entire chip in both the horizontal and vertical directions. Several non-uniform and directionally-biased architectures, however are fairly area-efficient provided that appropriate choices are made for the pin positions on the logic blocks and the logic array aspect ratio.Keywords
This publication has 6 references indexed in Scilit:
- Logic block and routing considerations for a new SRAM-based FPGA architecturePublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- Placement and routing tools for the Triptych FPGAIEEE Transactions on Very Large Scale Integration (VLSI) Systems, 1995
- FlowMap: an optimal technology mapping algorithm for delay optimization in lookup-table based FPGA designsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1994
- Field-Programmable Gate ArraysPublished by Springer Nature ,1992
- Optimization by Simulated AnnealingScience, 1983
- An Algorithm for Path Connections and Its ApplicationsIEEE Transactions on Electronic Computers, 1961