A programmable VLSI architecture for computing multiplication and polynomial evaluation modulo a positive integer

1 February 1988

journal article
Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Journal of Solid-State Circuits

Vol. 23 (1) , 204-207
https://doi.org/10.1109/4.280

Abstract

A programmable VLSI architecture with regular, modular, expansible features is designed for computing AB mod N, AB+C mode N, and polynomial evaluation modulo N. The size of the resultant circuit can be easily expanded to improve the security of cryptosystems without making any change to its control circuit. The computing procedures for all N throughout the range of 0<N<2/sup n-1/ are identical. Therefore, the circuit is well-suited for those systems in which the value of N is alternated frequently.

Keywords

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