Precise CMOS current sample/hold circuits using differential clock feedthrough attenuation techniques

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Abstract
New CMOS current samplehold (CSH) circuits ca- pable of overcoming the accuracy limitations in conventional cir- cuits without significantly reducing operating speed are proposed and analyzed. A novel differential clock feedthrough attenuation (DCFA) technique is developed to attenuate the signal-dependent clock feedthrough errors. Unlike conventional techniques, the DCFA circuit allows the use of dynamic mirror techniques, and results in no additional finite output resistance errors or device mismatch errors. The test chip of the proposed fully differential CSH circuit with multiple outputs bas been fabricated in 1.2-pm CMOS technology. Using a single 5-V power supply, experimental results show that the signal-dependent clock feedthrough error current is less than f0.4 pA for the input currents from -550 pA to 550 pA. The acquisition time for a 900-pA step transition to 0.1% settling accuracy is 150 ns. For a 410-pAP-, input at 250 kHz with the fabricated fully-differential CSH circuit clocked at 4 MHz, a total harmonic distortion of -60 dB, and a signal-to- noise ratio of 79 dB have been obtained. The active chip area and power consumption of the fabricated CSH circuit are 0.64 mm2 and 20 mW, respectively. Both simulation and experimental results have successfully verified the functions and performance of the proposed CSH circuits.

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