Quantifying Wafer Charging During Via Etch

24 August 2005

conference paper
Published by Institute of Electrical and Electronics Engineers (IEEE)

p. 30-33
https://doi.org/10.1109/ppid.1996.715196

Abstract

A CHARM/sup TM/-2 investigation of wafer charging during via etching shows that wafer surface conditions strongly influence the observed results. Under identical process conditions, bare wafers underestimate the charging results. When wafers are covered with patterned resist, much higher surface-substrate potentials and current densities are observed.

Keywords

ETCHING
EPROM
SURFACE CHARGING
CURRENT MEASUREMENT
THRESHOLD VOLTAGE
RESISTS
TESTING
VEHICLES
SENSOR PHENOMENA AND CHARACTERIZATION
CHARGE MEASUREMENT

This publication has 1 reference indexed in Scilit:

Modeling of oxide breakdown from gate charging during resist ashing
IEEE Transactions on Electron Devices, 1994