A 600MIPS 120mw 70μA leakage triple-CPU mobile application processor chip

30 August 2005

conference paper
Published by Institute of Electrical and Electronics Engineers (IEEE)

No. 01936530,p. 136-138
https://doi.org/10.1109/isscc.2005.1493906

Abstract

A triple-CPU mobile application processor is developed on an 8.95mm/spl times/8.95mm die in a 0.13/spl mu/m CMOS process. The IC integrates 3/spl times/ARM926 cores, a DSP several accelerators, as well as strong bus and memory interfaces. It consumes 120mW for digital TV, Web browser, and 30 graphics, and 250mW@200MHz for 600MIPS with full processing.

Keywords

SDRAM
ENERGY CONSUMPTION
DELAY
BANDWIDTH
THROUGHPUT
CELLULAR PHONES
APPLICATION SOFTWARE
PROGRAMMING
COSTS
DIGITAL SIGNAL PROCESSING CHIPS

This publication has 2 references indexed in Scilit:

A single-chip multiprocessor for smart terminals
IEEE Micro, 2000
C-based SoC design flow and EDA tools: an ASIC and system vendor perspective
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2000