A test generation system for path delay faults
- 7 January 2003
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
Abstract
A complete test pattern generation system for path delay faults is presented. The test pattern generator is based on PODEM using a 5-valued logic. Techniques to prune the search space for test pattern generation are proposed. Since the number of paths for test generation can be exponential in the number of lines in the network, criteria and efficient algorithms to prune the number of paths for test generation are presented. The test generation system is evaluated using the ISCAS combinational benchmark circuits.Keywords
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