A 2-mW Power Consumption Low Noise Amplifier in PD SOI CMOS Technology for 2.4 GHz Applications
- 1 January 2007
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
- p. 253-256
- https://doi.org/10.1109/smic.2007.322806
Abstract
This paper reviews and analyzes a fully integrated low-noise amplifier (LNA) for low-power and narrow-band applications using a cascode inductive source degeneration topology, with a body contacted transistor in 130 nm partially depleted CMOS SOI technology. Thanks to the SOI technology, the LNA shows only 2 mW power consumption when power gain of 10 dB and a noise figure of 3.1 dB at 2.4 GHz are measured for 1.2 V supply voltageKeywords
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