Delay Reduction Using Simulated Annealing
- 1 January 1986
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
Abstract
No abstract availableKeywords
This publication has 6 references indexed in Scilit:
- Macromodeling and Optimization of Digital MOS VLSI CircuitsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1986
- Simulated Annealing Without Rejected MovesIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1986
- The TimberWolf placement and routing packageIEEE Journal of Solid-State Circuits, 1985
- Algorithms for automatic transistor sizing in CMOS digital circuitsPublished by Association for Computing Machinery (ACM) ,1985
- An algorithm for CMOS timing and area optimizationIEEE Journal of Solid-State Circuits, 1984
- Delay and Power Optimization in VLSI CircuitsPublished by Institute of Electrical and Electronics Engineers (IEEE) ,1984