New design error modeling and metrics for design validation
- 2 January 2003
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
Abstract
When simulation is used for design verification, a subset of simulation input patterns is used, since exhaustive simulation is usually not practical. This produces uncertainty as to how much of the design has been verified. To provide a measure of the simulation pattern coverage based on design error modeling, a new simulation coverage metric is introduced. This measure is useful for obtaining insight into the actual level of design validation, since it provides more realistic results than those which are presently available.Keywords
This publication has 4 references indexed in Scilit:
- Modelling and simulation of design errorsPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2003
- An Implicit Enumeration Algorithm to Generate Tests for Combinational Logic CircuitsIEEE Transactions on Computers, 1981
- Diagnosis & Reliable Design of Digital SystemsPublished by Springer Nature ,1976
- Digital Logic Simulation in a Time-Based, Table-Driven EnvironmentComputer, 1975