A high-performance 0.1 μm CMOS with elevated salicide using novel Si-SEG process
- 23 November 2002
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
- No. 01631918,p. 99-102
- https://doi.org/10.1109/iedm.1997.649473
Abstract
High-performance 0.1 /spl mu/m CMOS devices with elevated salicide film for gate electrode and source/drain (S/D) regions and 80-nm gate side-wall have been demonstrated by a novel silicon selective epitaxial growth (SEG) process. Both junction leakage current and electrical bridging between the gate electrode and S/D regions are suppressed by this high-quality and highly-selective Si-SEG process. The elevated-salicide 0.1-/spl mu/m CMOS devices have high reliability and high drive current, and are suitable for future high-performance logic LSIs.Keywords
This publication has 4 references indexed in Scilit:
- A high performance 0.25 μm logic technology optimized for 1.8 V operationPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- A 0.05 μm-CMOS with ultra shallow source/drain junctions fabricated by 5 keV ion implantation and rapid thermal annealingPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- Low-resistance self-aligned Ti-silicide technology for sub-quarter micron CMOS devicesIEEE Transactions on Electron Devices, 1996
- Facet formation mechanism of silicon selective epitaxial layer by Si ultrahigh vacuum chemical vapor depositionJournal of Crystal Growth, 1994