CMOS sampler with 1 Gbit/s bandwidth and 25 ps resolution

30 December 2002

conference paper
Published by Institute of Electrical and Electronics Engineers (IEEE)

p. 27.5.1-27.5.4
https://doi.org/10.1109/cicc.1993.590806

Abstract

A technique and circuitry for real-time high-resolution sampling of a digital waveform are presented. This circuitry has been fabricated in 1.2 /spl mu/m CMOS technology, and test results show a bandwidth of up to 1 Gbit/s for the digital data and a sampling resolution externally adjustable between 25 ps and 250 ps. The fabricated circuit has shown sampling stability, monotonicity, and uniformity in sampling resolution.

Keywords

BANDWIDTH
SAMPLING METHODS
CLOCKS
LATCHES
INVERTERS
CIRCUITS
SIGNAL RESOLUTION
CMOS TECHNOLOGY
PROPAGATION DELAY
METASTASIS

This publication has 2 references indexed in Scilit:

Synthesis techniques for CMOS folded source-coupled logic circuits
IEEE Journal of Solid-State Circuits, 1992
A 30-MHz hybrid analog/digital clock recovery circuit in 2- mu m CMOS
IEEE Journal of Solid-State Circuits, 1990