A reconfigurable wafer scale array for image processing

Publisher Website

7 January 2003

conference paper
Published by Institute of Electrical and Electronics Engineers (IEEE)

https://doi.org/10.1109/wafer.1989.47558

Abstract

No abstract available

Keywords

This publication has 5 references indexed in Scilit:

Architectural yield optimization for WSI
IEEE Transactions on Computers, 1988
Wafer-Scale Integration of Systolic Arrays
IEEE Transactions on Computers, 1985
On Area and Yield Considerations for Fault-Tolerant VLSI Processor Arrays
IEEE Transactions on Computers, 1984
Fault-tolerant wafer-scale architectures for VLSI
ACM SIGARCH Computer Architecture News, 1982
Why systolic architectures?
Computer, 1982