A 33-ns 64-Mb DRAM
- 1 January 1991
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Journal of Solid-State Circuits
- Vol. 26 (11) , 1498-1505
- https://doi.org/10.1109/4.98964
Abstract
No abstract availableKeywords
This publication has 6 references indexed in Scilit:
- A 45 ns 16 Mb DRAM with triple-well structurePublished by Institute of Electrical and Electronics Engineers (IEEE) ,2003
- 3-dimensional stacked capacitor cell for 16 M and 64 M DRAMSPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2003
- A 33ns 64Mb DRAMPublished by Institute of Electrical and Electronics Engineers (IEEE) ,1991
- The impact of data-line interference noise on DRAM scalingIEEE Journal of Solid-State Circuits, 1988
- A Twisted Bit Line Technique for Multi-Mb DramsPublished by Institute of Electrical and Electronics Engineers (IEEE) ,1988
- An Experimental 16mb Dram with Transposed Data-Line StructurePublished by Institute of Electrical and Electronics Engineers (IEEE) ,1988