A Third-Generation 65nm 16-Core 32-Thread Plus 32-Scout-Thread CMT SPARC® Processor
- 1 February 2008
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE International Solid-State Circuits Conference
- No. 01936530,p. 82-83
- https://doi.org/10.1109/isscc.2008.4523067
Abstract
The goals for this high-end commercial microprocessor are high throughput and high single-thread performance, mainframe-class reliability, hardware transactional memory, and linear scalability. We show how these goals are met by the logical and physical design of this 2.3GHz 396mm2 16-core 32-thread plus 32-scout-thread microprocessor.Keywords
This publication has 3 references indexed in Scilit:
- Transactional memory for a modern microprocessorPublished by Association for Computing Machinery (ACM) ,2007
- A modern high-performance processor pipelinePublished by Association for Computing Machinery (ACM) ,2006
- High-Performance Throughput ComputingIEEE Micro, 2005