VLSI implementation of a 16*16 DCT
- 6 January 2003
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
Abstract
The implementation of a 16*16 discrete cosine transform (DCT) chip using a concurrent architecture is presented. The chip is designed for real-time processing of 14.3 MHz sampled video data. The architecture and accuracy studies for finite-wordlength processing are discussed. The chip was implemented, tested, and found to be fully functional. Possible variations are presented for multipurpose (variable transform sizes, forward-backward transform) applications.Keywords
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