Clocking and circuit design for a parallel I/O on a first-generation CELL processor
- 30 August 2005
- proceedings article
- Published by Institute of Electrical and Electronics Engineers (IEEE)
Abstract
No abstract availableThis publication has 3 references indexed in Scilit:
- The design and implementation of a first-generation CELL processorPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2005
- A 0.4-4-Gb/s CMOS quad transceiver cell using on-chip regulated dual-loop PLLsIEEE Journal of Solid-State Circuits, 2003
- A 2.4 Gb/s/pin simultaneous bidirectional parallel link with per-pin skew compensationIEEE Journal of Solid-State Circuits, 2000