Boolean decomposition in multi-level logic optimization
- 6 January 2003
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
Abstract
Multiple-valued Boolean minimization is proposed as a technique for identifying and extracting good Boolean factors which can be used as strong divisors to minimize the literal count and the area of a multilevel logic network. Given a two-level logic function, a subset of inputs to the function is selected such that the number of good Boolean factors contained in this subset of inputs is large. If the targeted implementation is a set of interconnected PLAs, the different cube combinations given by the subset of inputs are re-encoded to reduce the number of product terms in the logic function. A novel algorithm for the re-encoding is given that is based on the notion of partial satisfaction of constraints. Algorithms have been developed that identify a set of factors which maximally decrease the literal count of the logic network when they are used as strong divisors. Results obtained on several benchmark examples that illustrate the efficacy of the techniques are presented.Keywords
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