High-level synthesis of fault-tolerant ASICs

2 January 2003

conference paper
Published by Institute of Electrical and Electronics Engineers (IEEE)

Vol. 1, 419-422
https://doi.org/10.1109/iscas.1992.229924

Abstract

Methodologies for the high-level synthesis of fault-tolerant application-specific ICs (ASICs) that maximize performance in the presence of fault-tolerance and cost constraints are developed. The fault-tolerance constraints supported include number of faults per module (fault-masking constraint) and chip reliability (reliability constraint). Experience with the system shows that (a) it is feasible to automate design for fault-tolerance and (b) controlled interplay between cost, performance, and fault-tolerance, during high-level synthesis, helps synthesize high-quality and cost-effective fault-tolerant ASICs.

Keywords

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