The use of random simulation in formal verification

This publication has 4 references indexed in Scilit:

• Functional comparison of logic designs for VLSI circuits
  Published by Institute of Electrical and Electronics Engineers (IEEE) ,2003
• Efficient implementation of a BDD package
  Published by Institute of Electrical and Electronics Engineers (IEEE) ,2002
• Verity—A formal verification program for custom CMOS circuits
  IBM Journal of Research and Development, 1995
• Graph-Based Algorithms for Boolean Function Manipulation
  IEEE Transactions on Computers, 1986