Functional comparison of logic designs for VLSI circuits
- 7 January 2003
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
- p. 456-459
- https://doi.org/10.1109/iccad.1989.76990
Abstract
A method is described for circuit equivalence which proceeds by reducing the question of whether two circuits are equivalent to a number of a more easily answered questions concerning the equivalence of smaller, related circuits. The primary technical contribution is a technique for discovering internal equivalences and using them to show the equivalence of the outputs. The method involves the use of signatures to reduce the number of potentially equivalent signals, and the use of the min-cut algorithm to reduce the original problem to related problems with fewer independent inputs. The method can be used to extend the power of any given equivalence checking algorithm. The authors report the result of experiments evaluating their technique.Keywords
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