Redundancy for yield enhancement in the 3-D computer
- 7 January 2003
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
Abstract
No abstract availableKeywords
This publication has 4 references indexed in Scilit:
- The 3-D computerPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2003
- A review of fault-tolerant techniques for the enhancement of integrated circuit yieldProceedings of the IEEE, 1986
- Reconfigurable architectures for VLSI processing arraysProceedings of the IEEE, 1986
- A fault-tolerant 64K dynamic random-access memoryIEEE Transactions on Electron Devices, 1979