A 2 Gb/s 21 CH low-latency transceiver circuit for inter-processor communication

13 November 2002

conference paper
Published by Institute of Electrical and Electronics Engineers (IEEE)

p. 60-61
https://doi.org/10.1109/isscc.2001.912545

Abstract

A 20-data-channel transceiver with a control channel allows uncoded data transfer with 13 ns latency. A digital DLL with a ring-interpolator tracks phase with 20 ps resolution. A pre-emphasis driver enables 2 Gb/s transmission per channel over a 7 m cable at 1.5 V. The effective full-duplex bandwidth reaches 10 GB/s. Author(s) Tanahashi, T. NEC Corp., Tokyo, Japan Kurisu, M. ; Yamaguchi, H. ; Nedachi, T. ; Arai, M. ; Tomari, S. ; Matsuzaki, T. ; Nakamura, K. ; Fukaishi, M. ; Naramoto, S. ; Sato, T.

Keywords

TRANSCEIVERS
CIRCUITS
DELAY
CLOCKS
TRANSMITTERS
TIMING
SHIFT REGISTERS
SIGNAL GENERATORS
NATIONAL ELECTRIC CODE
SAMPLING METHODS

This publication has 1 reference indexed in Scilit:

A portable digital DLL architecture for CMOS interface circuits
Published by Institute of Electrical and Electronics Engineers (IEEE) ,2002