Exploiting hierarchy in VLSI design
- 1 January 1986
- book chapter
- Published by Springer Nature
- p. 180-193
- https://doi.org/10.1007/3-540-16766-8_16
Abstract
No abstract availableKeywords
This publication has 21 references indexed in Scilit:
- Hierarchical planarity testing algorithmsPublished by Springer Nature ,1986
- Efficient algorithms for finding minimum spanning forests of hierarchically defined graphsPublished by Springer Nature ,1986
- Hierarchical circuit verificationPublished by Association for Computing Machinery (ACM) ,1985
- A Switch-Level Model and Simulator for MOS Digital SystemsIEEE Transactions on Computers, 1984
- Hierarchical Layout VerificationPublished by Institute of Electrical and Electronics Engineers (IEEE) ,1984
- A Hiererachical, Error-Tolerant CompactorPublished by Institute of Electrical and Electronics Engineers (IEEE) ,1984
- A methodology for custom VLSI layoutIEEE Transactions on Circuits and Systems, 1983
- A Vertically Integrated VLSI Design EnvironmentPublished by Institute of Electrical and Electronics Engineers (IEEE) ,1983
- The complexity of compacting hierarchically specified layouts of integrated circuitsPublished by Institute of Electrical and Electronics Engineers (IEEE) ,1982
- Exploitation of Hierarchy in Analyses of Integrated Circuit ArtworkIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1982