A 60ns 4Mb CMOS DRAM with built-in self-test
- 1 January 1987
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
- Vol. XXX, 286-287
- https://doi.org/10.1109/isscc.1987.1157105
Abstract
No abstract availableKeywords
This publication has 3 references indexed in Scilit:
- An experimental 4Mb CMOS DRAMPublished by Institute of Electrical and Electronics Engineers (IEEE) ,1986
- An 85ns 1Mb DRAM in a plastic DIPPublished by Institute of Electrical and Electronics Engineers (IEEE) ,1985
- A 90ns 1Mb DRAM with multi-bit test modePublished by Institute of Electrical and Electronics Engineers (IEEE) ,1985