Effects of Interface Traps on Charge Retention Characteristics in Silicon-Quantum-Dot-Based Metal-Oxide-Semiconductor Diodes
- 1 January 1999
- journal article
- Published by IOP Publishing in Japanese Journal of Applied Physics
- Vol. 38 (1S)
- https://doi.org/10.1143/jjap.38.425
Abstract
We have demonstrated the effects of interface traps and defects on the charge retention characteristics in silicon-quantum-dot (Si-QDs)-based metal-oxide-semiconductor (MOS) memory structures. MOS diodes with various interface traps and defects introduced by thermal annealing treatment are investigated using a capacitance-voltage (C-V) measurement technique. The model of deep trapping centers including three-dimensional quantum confinement and Coulomb charge effects has been developed to successfully explain the observed long-term charge retention behaviors.Keywords
This publication has 8 references indexed in Scilit:
- Effects of traps on charge storage characteristics in metal-oxide-semiconductor memory structures based on silicon nanocrystalsJournal of Applied Physics, 1998
- Room temperature operation of a quantum-dot flash memoryIEEE Electron Device Letters, 1997
- A room-temperature silicon single-electron metal–oxide–semiconductor memory with nanoscale floating-gate and ultranarrow channelApplied Physics Letters, 1997
- Conductance measurements on P b centers at the (111) Si:SiO2 interfaceJournal of Applied Physics, 1996
- Single charge and confinement effects in nano-crystal memoriesApplied Physics Letters, 1996
- A silicon nanocrystals based memoryApplied Physics Letters, 1996
- Screening in Semiconductor Nanocrystallites and Its Consequences for Porous SiliconPhysical Review Letters, 1995
- Room-temperature single-electron memoryIEEE Transactions on Electron Devices, 1994