A Monte Carlo based circuit-level methodology for algorithmic design of MOS LSI static random logic circuits
- 1 October 1977
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Journal of Solid-State Circuits
- Vol. 12 (5) , 560-565
- https://doi.org/10.1109/JSSC.1977.1050955
Abstract
A Monte Carlo analysis is presented for the design of input gates in MOS LSI custom static random logic circuits implemented in NORs, NANDs, AOIs, OAIs, etc. The design approach is algorithmic and suited for CAD applications in multi-part-number logic chip design. The algorithms are derived and their usage illustrated for Weinberger chip layouts using circuit-level approximations, assumptions, and criteria.Keywords
This publication has 7 references indexed in Scilit:
- A high performance low power 2048-bit memory chip in MOSFET technology and its applicationIEEE Journal of Solid-State Circuits, 1976
- Subthreshold design considerations for insulated gate field-effect transistorsIEEE Journal of Solid-State Circuits, 1974
- Performance simulation with circuit level modelsPublished by Institute of Electrical and Electronics Engineers (IEEE) ,1974
- An analysis of the threshold voltage for short-channel IGFET'sSolid-State Electronics, 1973
- Algorithms for ASTAP--A network-analysis programIEEE Transactions on Circuit Theory, 1973
- Modeling and simulation of insulated-gate field-effect transistor switching circuitsIEEE Journal of Solid-State Circuits, 1968
- Large Scale Integration of MOS Complex Logic: A Layout MethodIEEE Journal of Solid-State Circuits, 1967