Matrix unit cell scheduler (MUCS) for input-buffered ATM switches
- 1 January 1998
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Communications Letters
- Vol. 2 (1) , 20-23
- https://doi.org/10.1109/4234.658616
Abstract
This paper presents a novel matrix unit cell scheduler (MUCS) for input-buffered asynchronous transfer mode (ATM) switches. The MUCS concept originates from a heuristic strategy that leads to an optimal solution for cell scheduling. Numerical analysis indicates that input-buffered ATM switches scheduled by MUCS can utilize nearly 100% of the available link bandwidth. A transistor-level MUCS circuit has been designed and verified using HSPICE. The circuit features a regular structure, minimal interconnects, and a low transistor count. HSPICE simulation indicates that using 2-/spl mu/m CMOS technology, the MUCS circuit can operate at clock frequency of 100 MHz.Keywords
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