Spare processor allocation for fault tolerance in torus-based multicomputers
- 23 December 2002
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
Abstract
Some fault-tolerant architectures use the spare nodes or links to replace the faulty components. This paper gives solutions to spare processor placement problem for torus based networks. Optimal 1-hop spare processor placement methods for multi-dimensional tori and t-hop placement methods for 2D tori are described. In the presence of node failures, a system reconfiguration scheme using spare nodes is also given.Keywords
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