The use and evaluation of yield models in integrated circuit manufacturing
- 1 May 1990
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Semiconductor Manufacturing
- Vol. 3 (2) , 60-71
- https://doi.org/10.1109/66.53188
Abstract
No abstract availableThis publication has 10 references indexed in Scilit:
- Critical area and critical levels calculation in IC yield modelingIEEE Transactions on Electron Devices, 1988
- On yield, fault distributions, and clustering of particlesIBM Journal of Research and Development, 1986
- The effects of wafer to wafer defect density variations on integrated circuit defect and fault distributionsIBM Journal of Research and Development, 1985
- LSI Yield Modeling and Process MonitoringIBM Journal of Research and Development, 1976
- Applying a composite model to the IC yield problemIEEE Journal of Solid-State Circuits, 1974
- Defect density distribution for LSI yield calculationsIEEE Transactions on Electron Devices, 1973
- Analysis on yield of integrated circuits and a new expression for the yieldElectrical Engineering in Japan, 1972
- A new look at yield of integrated circuitsProceedings of the IEEE, 1970
- High-yield-processed bipolar LSI arraysPublished by Institute of Electrical and Electronics Engineers (IEEE) ,1968
- Cost-size optima of monolithic integrated circuitsProceedings of the IEEE, 1964