A 200 MHz quadrature digital synthesizer/mixer in 0.8 μm CMOS

This publication has 9 references indexed in Scilit:

• The optimization of direct digital frequency synthesizer performance in the presence of finite word length effects
  Published by Institute of Electrical and Electronics Engineers (IEEE) ,2003
• Low-latency, high-speed numerically controlled oscillator using progression-of-states technique
  IEEE Journal of Solid-State Circuits, 1992
• A 150-MHz direct digital frequency synthesizer in 1.25- mu m CMOS with -90-dBc spurious performance
  IEEE Journal of Solid-State Circuits, 1991
• A 200-MHz all-digital QAM modulator and demodulator in 1.2- mu m CMOS for digital radio applications
  IEEE Journal of Solid-State Circuits, 1991
• High-speed CMOS circuit technique
  IEEE Journal of Solid-State Circuits, 1989
• An Analysis of the Output Spectrum of Direct Digital Frequency Synthesizers in the Presence of Phase-Accumulator Truncation
  Published by Institute of Electrical and Electronics Engineers (IEEE) ,1987
• A digital frequency synthesizer
  IEEE Transactions on Audio and Electroacoustics, 1971
• Conditional-Sum Addition Logic
  IEEE Transactions on Electronic Computers, 1960
• A SIGNED BINARY MULTIPLICATION TECHNIQUE
  The Quarterly Journal of Mechanics and Applied Mathematics, 1951