Low-latency, high-speed numerically controlled oscillator using progression-of-states technique
- 1 January 1992
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Journal of Solid-State Circuits
- Vol. 27 (1) , 113-117
- https://doi.org/10.1109/4.109564
Abstract
No abstract availableKeywords
This publication has 6 references indexed in Scilit:
- A 7 MHz 24-bit pipelined accumulator in 1.2- mu m CMOS for application as a numerically controlled oscillatorPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- Configurable demodulator ASIC for the TDRSS communication systemPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- A high-speed direct frequency synthesizerIEEE Journal of Solid-State Circuits, 1990
- Digitally controlled oscillatorIEEE Journal of Solid-State Circuits, 1989
- A direct digital synthesizer with 100-MHz output capabilityIEEE Journal of Solid-State Circuits, 1988
- A digital frequency synthesizerIEEE Transactions on Audio and Electroacoustics, 1971