Syndrome-Testing of " Syndrome-Untestable" Combinational Circuits
- 1 August 1981
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Computers
- Vol. C-30 (8) , 606-608
- https://doi.org/10.1109/TC.1981.1675849
Abstract
In [1] and [2] a method of designing syndrome-testable combinational circuits was described. It was shown that, in general, syndrome-testable combinational circuits require some pin-penalty and maybe some logic for producing the testable design.Keywords
This publication has 4 references indexed in Scilit:
- Correction to "Syndrome-Testable Design of Combinational Circuits"IEEE Transactions on Computers, 1980
- Syndrome-Testable Design of Combinational CircuitsIEEE Transactions on Computers, 1980
- A Practical Approach to Fault Detection in Combinational NetworksIEEE Transactions on Computers, 1978
- An Efficient Algorithm for Generating Complete Test Sets for Combinational Logic CircuitsIEEE Transactions on Computers, 1971