Processing technology and AC/DC characteristics of linear compatible I/sup 2/L
- 1 August 1976
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Journal of Solid-State Circuits
- Vol. 11 (4) , 478-485
- https://doi.org/10.1109/JSSC.1976.1050762
Abstract
The processing, a.c. and d.c. characteristics of I/SUP 2/L structures integrated with common analog circuit elements are studied. Since the required breakdown voltage of the analog circuitry normally dictates the resistivity and thickness of the silicon epitaxial layer, the authors studied the parametric performance of the I/SUP 2/L structure for common linear circuit voltages. Design criteria, processing, and device performance are presented for I/SUP 2/L structures built on several different types of material. The I/SUP 2/L performance achieved in the linear compatible technology easily allowed a fan-out of four and gate propagation delay less than 50 ns with standard device breakdowns of 20 V; but fan-out is limited to three and gate delay to 100 ns for the process which attained 30-V breakdowns.Keywords
This publication has 5 references indexed in Scilit:
- Device physics of integrated injection logicIEEE Transactions on Electron Devices, 1975
- The effect of isolation regions on the current gain of inverse NPN-transistors used in Integrated Injection Logic (I2L)Published by Institute of Electrical and Electronics Engineers (IEEE) ,1974
- The injection model-a structure-oriented model for merged transistor logic (MTL)IEEE Journal of Solid-State Circuits, 1974
- On the measurement of the specific ‘emitter efficiency factor in bipolar transistors’Solid-State Electronics, 1972
- Integrated injection logic: a new approach to LSIIEEE Journal of Solid-State Circuits, 1972