A fully integrated 0.5-5.5 GHz CMOS distributed amplifier
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- 1 February 2000
- journal article
- research article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Journal of Solid-State Circuits
- Vol. 35 (2) , 231-239
- https://doi.org/10.1109/4.823448
Abstract
A fully integrated 0.5-5.5-GHz CMOS-distributed amplifier is presented. The amplifier is a four stage design fabricated in a standard 0.6-/spl mu/m three-layer metal digital-CMOS process. The amplifier has a unity-gain cutoff frequency of 5.5 GHz, and a gain of 6.5 dB, with a gain flatness of /spl plusmn/1.2 dB over the 0.5-4 GHz band. Input and output are matched to 50 /spl Omega/, with worst-case return losses on the input and output of -7 and -10 dB, respectively. Power dissipation is 83.4 mW from a 3.0 V supply, input-referred 1-dB compression point varies from +6 dBm at 1 GHz to 8.8 dBm at 5 GHz. From a circuit standpoint, the fully integrated nature of the amplifier on the given substrate results in a heavily parasitic-laden design. Discussion emphasis is therefore placed on the practical design, modeling, and CAD optimization techniques used in the design process.Keywords
This publication has 19 references indexed in Scilit:
- S-band distributed raman fiber amplifierPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2012
- Monolithic CMOS distributed amplifier and oscillatorPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2003
- Fully-integrated CMOS RF amplifiersPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2003
- CMOS distributed amplifier design using CAD optimization techniquesPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2003
- A simulated annealing algorithm for optimizing RF power efficiency in coupled-cavity traveling-wave tubesIEEE Transactions on Electron Devices, 1997
- Optimization and adaptation of discrete-valued digital filter parameters by simulated annealingIEEE Transactions on Signal Processing, 1994
- Simulated annealing algorithms: an overviewIEEE Circuits and Devices Magazine, 1989
- The Declining Drain Line Lengths Circuit--A Computer Derived Design Concept Applied to a 2 26.5-GHz Distributed AmplifierIEEE Transactions on Microwave Theory and Techniques, 1986
- A DC-12 GHz Monolithic GaAsFET Distributed AmplifierIEEE Transactions on Microwave Theory and Techniques, 1982
- A Monolithic GaAs 1-13-GHz Traveling-Wave AmplifierIEEE Transactions on Microwave Theory and Techniques, 1982