System-level fault modeling and test pattern generation with process algebras
- 31 December 2002
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
Abstract
No abstract availableKeywords
This publication has 19 references indexed in Scilit:
- Synthesis and simulation of digital systems containing interacting hardware and software componentsPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2003
- Increasing fault coverage for synchronous sequential circuits by the multiple observation time test strategyPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- Efficient implementation of a BDD packagePublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- An approach to sequential circuit diagnosis based on formal verification techniquesJournal of Electronic Testing, 1993
- Translating system specifications to VHDLPublished by Institute of Electrical and Electronics Engineers (IEEE) ,1991
- A unified high-level Petri net formalism for time-critical systemsIEEE Transactions on Software Engineering, 1991
- STATEMATE: a working environment for the development of complex reactive systemsIEEE Transactions on Software Engineering, 1990
- Statecharts: a visual formalism for complex systemsScience of Computer Programming, 1987
- Testing equivalences for processesTheoretical Computer Science, 1984
- Test Generation for MicroprocessorsIEEE Transactions on Computers, 1980