Device modeling of ferroelectric capacitors

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Abstract
A physically based methodology is developed for modeling the behavior of electrical circuits containing nonideal ferroelectric capacitors. The methodology is illustrated by modeling the discrete ferroelectric capacitor as a stacked dielectric structure, with switching ferroelectric and nonswitching dielectric layers. Electrical properties of a modified Sawyer–Tower circuit are predicted by the model. Distortions of hysteresis loops due to resistive losses as a function of input signal frequency are accurately predicted by the model. The effect of signal amplitude variations predicted by the model also agree with experimental data. The model is used as a diagnostic tool to demonstrate that cycling degradation, at least for the sample investigated, cannot be modeled by the formation of nonswitching dielectric layer(s) or the formation of conductive regions near the electrodes, but is consistent with a spatially uniform reduction in the number of switching dipoles.

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