A 500MHz multi-banked compilable DRAM macro with direct write and programmable pipelining

28 September 2004

conference paper
Published by Institute of Electrical and Electronics Engineers (IEEE)

No. 01936530,p. 204-523
https://doi.org/10.1109/isscc.2004.1332665

Abstract

A 500MHz compiled DRAM macro fabricated in 90nm logic-based process is presented. The random bank cycle is reduced by 50% over the previous generation through segmentation and a direct write scheme. 500MHz operation is achieved with a configurable 4-stage pipeline.

Keywords

RANDOM ACCESS MEMORY
PIPELINE PROCESSING
KERNEL
WRITING
APPLICATION SPECIFIC INTEGRATED CIRCUITS
LOGIC ARRAYS
MICROELECTRONICS
FOUNDRIES
INTERLEAVED CODES
AVAILABILITY

This publication has 2 references indexed in Scilit:

A 300MHz multi-banked, eDRAM macro featuring GND sense, bit-line twisting and direct reference cell write
Published by Institute of Electrical and Electronics Engineers (IEEE) ,2005
A high density memory for SoC with a 143MHz SRAM interface using sense-synchronized-read/write
Published by Institute of Electrical and Electronics Engineers (IEEE) ,2003