A pipelined 5MHz 9b ADC
- 1 January 1987
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
- Vol. XXX, 210-211
- https://doi.org/10.1109/isscc.1987.1157169
Abstract
This paper will report on a 5Msamples/s 9b analog to digital converter in a 3μm CMOS process, which requires 3500 square mils, consumes 18mW, has an Input capacitance of 3pF and uses a fully differential architecture. Digital error correction makes the converter insensitive to comparator offset errors.Keywords
This publication has 4 references indexed in Scilit:
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- A high-performance micropower switched-capacitor filterIEEE Journal of Solid-State Circuits, 1985
- CMOS 8b 25MHz flash ADCPublished by Institute of Electrical and Electronics Engineers (IEEE) ,1985
- Full-speed testing of A/D convertersIEEE Journal of Solid-State Circuits, 1984