A buried p-layer self-aligned process for high-yield LSI circuits
- 13 January 2003
- proceedings article
- Published by Institute of Electrical and Electronics Engineers (IEEE)
Abstract
No abstract availableKeywords
This publication has 2 references indexed in Scilit:
- A 5.1-GHz 1.9-mW GaAs binary frequency dividerIEEE Electron Device Letters, 1989
- Buried p-layer SAINT for very high-speed GaAs LSI's with submicrometer gate lengthIEEE Transactions on Electron Devices, 1985