CrossCheck-a practical solution for ASIC testability

Abstract
It is noted that testing ASICs (application-specific integrated circuits) has become a significant problem for engineers; manual generation of test patterns is too time consuming, and automatic generation of test patterns is very difficult, if not impossible, without imposing significant overheads on the design. It is shown that this challenge can be addressed by an innovative solution called CrossCheck. The CrossCheck method fundamentally solves the problem by using a combination of software and hardware techniques. The hardware portion of the technology involves modifying the base array of an ASIC such that it contains a structure similar to a bed of nails. This embedded probe structure provides massive observability within the design, which in turn makes it inherently testable. The software can then take advantage of this testability by providing a set of high-performance tools (typically 40 times faster) which will fault simulate/test generate a broad range of manufacturing defects, including transistor opens and shorts or net opens and shorts. The authors give an overview of the technology and then describe probable defects which may occur in CMOS. They conclude that adoption of CrossCheck allows unprecedented levels of fault coverage and chip or board diagnosis to be achieved.

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