Cache performance of the integer SPEC benchmarks on a RISC
- 1 May 1990
- journal article
- Published by Association for Computing Machinery (ACM) in ACM SIGARCH Computer Architecture News
- Vol. 18 (2) , 53-68
- https://doi.org/10.1145/88237.88243
Abstract
SPEC is a new set of benchmark programs designed to measure a computer system's performance. The performance measured by benchmarks is strongly affected by the existence and configuration of cache memory. In this paper we evaluate the cache miss ratio of the Integer SPEC benchmarks. We show that the cache miss ratio depends strongly on the program, and that large caches are not completely exercised by these benchmarks.Keywords
This publication has 6 references indexed in Scilit:
- Evaluating associativity in CPU cachesIEEE Transactions on Computers, 1989
- APLA NewsletterPoLAR: Political and Legal Anthropology Review, 1989
- A case for direct-mapped cachesComputer, 1988
- Line (Block) Size Choice for CPU Cache MemoriesIEEE Transactions on Computers, 1987
- How not to lie with statistics: the correct way to summarize benchmark resultsCommunications of the ACM, 1986
- Cache MemoriesACM Computing Surveys, 1982