An experimental 4 Mb flash EEPROM with sector erase
- 1 April 1991
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Journal of Solid-State Circuits
- Vol. 26 (4) , 484-491
- https://doi.org/10.1109/4.75043
Abstract
No abstract availableKeywords
This publication has 4 references indexed in Scilit:
- An experimental 4 Mb CMOS EEPROM with a NAND structured cellPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2003
- A 4 Mb 5 V-only flash EEPROM with sector erasePublished by Institute of Electrical and Electronics Engineers (IEEE) ,1990
- A process technology for a 5-volt only 4 Mb flash EEPROM with an 8.6 UM2 cellPublished by Institute of Electrical and Electronics Engineers (IEEE) ,1990
- A 256-kbit flash E/SUP 2/PROM using triple-polysilicon technologyIEEE Journal of Solid-State Circuits, 1987