Minimal area merger of finite state machine controllers
- 2 January 2003
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
Abstract
The authors present techniques for merging a pair of finite state machines (FSMs) that control the data-path circuitry on a chip. In particular, these techniques can be used to merge FSMs that control the functional and test circuitry in the data path. An A* algorithm is used to obtain the state transition table of the merged controller, and then standard synthesis tools are used for state assignment and logic minimization. The procedure targets either two-level or multilevel logic implementation. Compared to implementing the functional and test controllers separately, it is shown that merging the controllers leads to significant savings in logic area. For multilevel implementation, the technique produces merged machines that have on average 20% less factored form literals than the machines produced by an existing state minimizer.Keywords
This publication has 7 references indexed in Scilit:
- Synthesis of optimal 1-hot coded on-chip controllers for BIST hardwarePublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- Exact algorithms for output encoding, state assignment, and four-level Boolean minimizationIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1991
- NOVA: state assignment of finite state machines for optimal two-level logic implementationIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1990
- Decomposition and factorization of sequential finite state machinesIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1989
- MUSTANG: state assignment of finite state machines targeting multilevel logic implementationsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1988
- MIS: A Multiple-Level Logic Optimization SystemIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1987
- Optimal State Assignment for Finite State MachinesIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1985