Collision detection VLSI processor for intelligent vehicles based on efficient coordinate transformation scheme
- 23 December 2002
- proceedings article
- Published by Institute of Electrical and Electronics Engineers (IEEE)
- Vol. 2, 755-760
- https://doi.org/10.1109/iecon.1996.565972
Abstract
No abstract availableKeywords
This publication has 8 references indexed in Scilit:
- Collision detection VLSI processor for intelligent vehicles based on a hierarchical obstacle representationPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- A 288-kb fully parallel content addressable memory using a stacked-capacitor cell structureIEEE Journal of Solid-State Circuits, 1992
- Robot Motion PlanningPublished by Springer Nature ,1991
- A proposed structure of a 4 Mbit content-addressable and sorting memoryPublished by Institute of Electrical and Electronics Engineers (IEEE) ,1990
- A novel representation for planning 3-D collision-free pathsIEEE Transactions on Systems, Man, and Cybernetics, 1990
- A simple motion-planning algorithm for general robot manipulatorsIEEE Journal on Robotics and Automation, 1987
- Conventional controller design for industrial robots — A tutorialIEEE Transactions on Systems, Man, and Cybernetics, 1983
- The CORDIC Trigonometric Computing TechniqueIRE Transactions on Electronic Computers, 1959