Experimental verification of row-by-row variable V/sub DD/ scheme reducing 95% active leakage power of SRAM's

27 July 2005

conference paper
Published by Institute of Electrical and Electronics Engineers (IEEE)

p. 162-165
https://doi.org/10.1109/vlsic.2005.1469356

Abstract

Low-power SRAM has become a critical component in recent VLSI systems. This paper reports an SRAM reducing 95% of active leakage power. The SRAM is successfully implemented and reliably measured for the first time, with self-aligned timing generation to avoid malfunction during V/sub DD/ transition. The cycle time overhead is 9%, and the area overhead is 3.5%.

Keywords

RANDOM ACCESS MEMORY
VOLTAGE
TIMING
CIRCUITS
VERY LARGE SCALE INTEGRATION
POWER ENGINEERING AND ENERGY
COLLABORATION
POWER SYSTEM RELIABILITY
TIME MEASUREMENT
PROPOSALS

This publication has 1 reference indexed in Scilit:

16.7 fA/cell tunnel-leakage-suppressed 16 Mb SRAM for handling cosmic-ray-induced multi-errors
Published by Institute of Electrical and Electronics Engineers (IEEE) ,2003